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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC941/D
Low Voltage 1:27 Clock Distribution Chip
The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 27 outputs are LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet.
MPC941
LOW VOLTAGE 3.3V/2.5V 1:27 CLOCK DISTRIBUTION CHIP
* * * * * * *
LVPECL or LVCMOS Clock Input 250ps Maximum Output-to-Output Skew Drives Up to 54 Independent Clock Lines Maximum Output Frequency of 250MHz High Impedance Output Enable 48-Lead LQFP Packaging 3.3V or 2.5V VCC Supply Voltage
FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-02
With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated 50 transmission lines. With this capability, the MPC941 has an effective fanout of 1:54. With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. The MPC941 is fully 3.3V and 2.5V compatible. The 48-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 48-lead LQFP has a 7x7mm body size.
02/01
(c) Motorola, Inc. 2001
1
REV 4
MPC941
LOGIC DIAGRAM
PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel pulldown pulldown Q26 OE pulldown 0 1 25 Q1-Q25
Q0
pulldown
Pinout: 48-Lead QFP (Top View)
GND GND VCC VCC
25
Q10
Q12
Q13
Q14
27
VCC Q7 Q6 Q5 GND Q4 Q3 VCC Q2 Q1 Q0 GND
37 38 39 40 41 42 43 44 45 46 47 48
36
35
34
33
32
31
30
29
28
Q15
26
Q11
Q8
Q9
24 23 22 21 20
GND Q16 Q17 Q18 VCC Q19 Q20 GND Q21 Q22 Q23 VCC
FUNCTION TABLE
LVCMOS_CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK
MPC941
19 18 17 16 15 14 13
1
2
3
4
5
6
7
8
9
10
11
12
LVCMOS_CLKSEL
LVCMOS_CLK
PECL_CLK
PECL_CLK
VCC
VCC
GND
Table 1: PIN CONFIGURATIONS
Pin PECL_CLK, PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel OE GND VCC Q0 - Q26 Output I/O Input Input Input Input Type LVPECL LVCMOS LVCMOS LVCMOS Supply Supply LVCMOS Function LVPECL differential reference clock inputs Alternative reference clock input Input reference clock select Output tristate control Negative voltage supply output bank (GND) Positive voltage supply Clock outputs
MOTOROLA
GND 2
Q26
Q25
Q24
OE
TIMING SOLUTIONS DL207 -- Rev 0
MPC941
Table 2: ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C
* Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 3: DC CHARACTERISTICS (VCC = 3.3V
Symbol VIH VIL IIN VPP VCMR VOH VOL IOZ ZOUT CPD CIN ICCQ VTT Characteristics Input high voltage Input low voltage Input current Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output tristate leakage current Output impedance Power Dissipation Capacitance Input capacitance Maximum Quiescent Supply Current Output termination voltage
5%, TA = -40 to +85C)
Min Typ Max VCC + 0.3 0.8 120a Unit V V A mV VCC-0.8 V V 0.55 0.40 100 14 - 17 7-8 4.0 5 VCC/2 10 V V A LVPECL LVPECL IOH=-24 mAb IOL= 24mA b IOL=12mA Condition LVCMOS LVCMOS 2.0 -0.3 500 1.2 2.4
LVCMOS_CLK LVCMOS_CLK PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK
W
pF pF mA V
Per Output All VCC Pins
a. Input pull-up / pull-down resistors influence input current. b. The MPC941 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
Table 4: AC CHARACTERISTICS (VCC = 3.3V
Symbol fMAX tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) tsk(PP) tsk(PP) DCQ Characteristics Maximum Output Frequency LVCMOS_CLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time
5%, TA = -40 to +85C)a
Min 0 1.2 0.9
Typ
Max 250b 1.0c
Unit MHz ns ns ns ns ns
Condition 0.8 to 2.0V
PECL_CLK to any Q LVCMOS_CLK to any Q
1.8 1.5
2.6 2.3
Output-to-output Skew PECL_CLK to any Q LVCMOS_CLK to any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q Output Duty Cycle PECL_CLK to any Q LVCMOS_CLK to any Q 45 45
125 125
250 250 1000 1000 1400 1400
ps ps ps ps ps % % For a given TA and VCC, any Q For any TA, VCC and Q DCREF = 50% DCREF = 50%
50 50
60 55
tr, tf Output Rise/Fall Time 0.2 1.0 ns 0.55 to 2.4V a. AC characteristics apply for parallel output termination of 50 to VTT. b. AC characteristics are guaranteed up to fmax. Please refer to applications section for information on power consumption versus operating frequency and thermal management. c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941.
TIMING SOLUTIONS DL207 -- Rev 0
3
MOTOROLA
MPC941
Table 5: DC CHARACTERISTICS (VCC = 2.5V
Symbol VIH VIL IIN VPP VCMR VOH VOL IOZ ZOUT CPD CIN ICCQ Characteristics Input high voltage Input low voltage Input current Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output tristate leakage current Output impedance Power Dissipation Capacitance Input capacitance Maximum Quiescent Supply Current 18 - 20 7-8 4.0 5 10 PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK 500 1.1 1.8 0.6 100 VCC-0.7 LVCMOS_CLK LVCMOS_CLK
5%, TA = -40 to +85C)
Min 1.7 -0.3 Typ Max VCC + 0.3 0.7 120a Unit V V A mV V V V A LVPECL LVPECL IOH=-15 mAb IOL= 15 mAb Condition LVCMOS LVCMOS
W
pF pF mA
Per Output
All VCC Pins
VTT Output termination voltage VCC/2 V a. Input pull-up / pull-down resistors influence input current. b. The MPC941 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
Table 6: AC CHARACTERISTICS (VCC = 2.5V
Symbol fMAX tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) tsk(PP) tsk(PP) DCQ Characteristics Maximum Output Frequency LVCMOS_CLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time
5%, TA = -40 to +85C)a
Min 0 Typ Max 250b 1.0c 1.3 1.0 2.1 1.8 2.9 2.6 Unit MHz ns ns ns ns ns 125 125 250 250 1200 1200 1600 1600 45 45 50 50 60 55 ps ps ps ps ps % % For a given TA and VCC, any Q For any TA, VCC and Q DCREF = 50% DCREF = 50% 0.7 to 1.7V Condition
PECL_CLK to any Q LVCMOS_CLK to any Q
Output-to-output Skew PECL_CLK to any Q LVCMOS_CLK to any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q Output Duty Cycle PECL_CLK to any Q LVCMOS_CLK to any Q
tr, tf Output Rise/Fall Time 0.2 1.0 ns 0.6 to 1.6V a. AC characteristics apply for parallel output termination of 50 to VTT. b. AC characteristics are guaranteed up to fmax. Please refer to the applications section for information on power consumption versus operating frequency and thermal management. c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941.
MOTOROLA
4
TIMING SOLUTIONS DL207 -- Rev 0
MPC941
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC941 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions data book (DL207/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC941 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC941 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC941 OUTPUT BUFFER IN
14
match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50 || 50 Rs = 36 || 36 Ro = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5 ZO = 50 OutA
RS = 36
0 2 4 6 8 TIME (nS) 10 12 14
MPC941 OUTPUT BUFFER IN
14
Figure 2. Single versus Dual Waveforms
RS = 36 ZO = 50 OutB0
RS = 36
ZO = 50 OutB1
Figure 1. Single versus Dual Transmission Lines The waveform plots of Figure 2 "Single versus Dual Waveforms" show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC941 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC941. The output waveform in Figure 2 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3 "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC941 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 3. Optimized Dual Line Termination
TIMING SOLUTIONS DL207 -- Rev 0
5
MOTOROLA
MPC941
Power Consumption of the MPC941 and Thermal Management The MPC941 AC specification is guaranteed for the entire operating frequency range up to 250 MHz. The MPC941 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperture, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC941 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 7: Die junction temperature and MTBF
Junction temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0
In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 7, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC941 in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 7. Rthja can be derived from Table 8. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below.
Table 8: Thermal package impedance of the 48ld LQFP
Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), K/W 78 68 59 56 54 53
Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC941 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC941 is represented in equation 1. Where ICCQ is the static current consumption of the MPC941, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC941). The MPC941 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. P TOT
If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC941. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to a estimated MTBF of 9.1 years (4 years), a supply voltage of either 3.3V or 2.5V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. CL
M
+
I CCQ
)V @f
CC
CLOCK
@ N@C )
PD
@V
OH
CC
Equation 1
P TOT
+V @
CC
I CCQ
)V @f
CC
CLOCK
@ N@C )
PD
CL
M
)
thja
DC Q
P
@ I @ V * V ) 1 * DC @ I @ V
CC OH Q OL
OL
Equation 2
TJ
+T )P @R
A TOT 2 CC
Equation 3
f CLOCK,MAX
1 +C @N@V @
PD
T J,MAX T A R thja
* * I @V
CCQ
CC
Equation 4
MOTOROLA
6
TIMING SOLUTIONS DL207 -- Rev 0
MPC941
300 TA = 55C OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 400 300 200 IFPM, CONVECTION 100 0 fMAX (AC) 250 TA = 55C 200 TA = 65C 150 100 50 0 TA = 75C TA = 85C TA = 65C TA = 75C TA = 85C 300 TA = 45C fMAX (AC) TA = 35C
Safe operation
Safe operation
300 200 IFPM, CONVECTION 100 0
500
400
Figure 4. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines
Figure 5. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line
300 OPERATING FREQUENCY (MHz) 250 200 fMAX (AC)
300 TA = 65C OPERATING FREQUENCY (MHz) 250 TA = 65C 200 150 100 TA = 75C TA = 85C TA = 75C TA = 85C TA = 55C fMAX (AC) TA = 45C
150 100
Safe operation
50 0 500 400 300 200 IFPM, CONVECTION 100 0
Safe operation
50 0 500 400 300 200 IFPM, CONVECTION 100 0
Figure 6. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines
Figure 7. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, 4 pF load per line
TIMING SOLUTIONS DL207 -- Rev 0
7
MOTOROLA
MPC941
300 OPERATING FREQUENCY (MHz) 250 200 150 100 fMAX (AC) TA = 85C OPERATING FREQUENCY (MHz) TA = 75C 300 TA = 65C 250 200 150 100 TA = 85C fMAX (AC) TA = 75C
Safe operation
50 0 500 400 300 200 IFPM, CONVECTION 100 0
Safe operation
50 0 500 400 300 200 IFPM, CONVECTION 100 0
Figure 8. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, driving series terminated transmission lines
Figure 9. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, 4 pF load per line
300 OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 400 300 200 IFPM, CONVECTION 100 0 fMAX (AC) TA = 85C OPERATING FREQUENCY (MHz)
300 250 200 150 100 50 0 500 400 300 200 IFPM, CONVECTION 100 0 fMAX (AC) TA = 75C
TA = 85C
Safe operation
Safe operation
Figure 10. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, driving series terminated transmission lines
Figure 11. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, 4 pF load per line
MOTOROLA
8
TIMING SOLUTIONS DL207 -- Rev 0
MPC941
DUT MPC941 Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 12. LVCMOS_CLK MPC941 AC test reference for Vcc = 3.3V and Vcc = 2.5V
DUT MPC941 Differential Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 13. PECL_CLK MPC941 AC test reference for Vcc = 3.3V and Vcc = 2.5V
VCC VCC VCC VCC
PECL_CLK PECL_CLK VPP VCMR VCC VCC
LVCMOS_CLK
B2 B2
GND
Q tPD
B2
Q
GND tPD
GND
Figure 14. LVPECL Propagation delay (tPD) test reference
VCC VCC tP T0 DC = tP /T0 x 100%
Figure 15. LVCMOS Propagation delay (tPD) test reference
VCC VCC
B2
B2 B2
GND
GND VOH VCC
GND tSK(O)
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device
Figure 16. Output Duty Cycle (DC)
VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V
Figure 17. Output-to-output Skew tSK(O)
VCC=3.3V 2.0 0.8 tF tR VCC=2.5V 1.7V 0.7V
Figure 18. Output Transition Time Test Reference
Figure 19. Input Transition Time Test Reference
TIMING SOLUTIONS DL207 -- Rev 0
9
MOTOROLA
MPC941
OUTLINE DIMENSIONS
FA SUFFIX PLASTIC QFP PACKAGE CASE 932-02 ISSUE E
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1_ 5_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080
SECTION AE-AE
MOTOROLA
EEE CCC EEE CCC EEE CCC
F D
M
C
E
AC T-U Z H DETAIL AD AA W K L_
10
0.250
N
J
TIMING SOLUTIONS DL207 -- Rev 0
MPC941
NOTES
TIMING SOLUTIONS DL207 -- Rev 0
11
MOTOROLA
MPC941
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12
TIMING SOLUTIONS MPC941/D DL207 -- Rev 0

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